My job description:
 

To forward the project, I'm often asked to:

  • Design timing critical parts or blocks with asynchronous interfaces.
  • Handle tape-out and contacts with vendor.
  • Setting up synthesis tools and handle various DFT issues.
  • Hold small in-house courses. See a list below.
  • Encapsulate vendor specific tools and design flows
    in order to simplify the block design flow.
  • Last, but maybe the most important function, I usually
    work as "the helpful old guy that you ask when you
    can't find a solution or why something doesn't work".
   
  Some courses I've designed and held:
  Connecting over clock domains
 		Setup/hold, metastability, asynchronous and isochronous inputs, double-clocking, double-buffering, fifos, circular buffers. A structured approach to inter-clock domain communication. Clock: gating, dividing and multiplication. Clock handling and limitations in FPGAs and ASICs. 2 h lecture.
 
  Some things simulation and synthesis
courses do not teach.
 		Block- and chip-level design flows. Back-end design flow. Floorplanning and clock tree design. PVT variation space and levels of simulation accuracy. Deep sub-micron delay calculation. Synthesis scripting and setup for successful layout. Basics of static timing analyses. 3 x 2 h lectures.
 
  Verilog workshop When several design-entry tools are available and engineer experience vary:  the style, look, feel, testability and error-prone-ness of the code differs a lot even within a design group. 

In this workshop all participants solve the same problem and then we go through all solutions giving (usually) constructive comments. Very efficient way to improve tool usage and enhance understanding of code style issues. Up to 6 h own work + 2 hour workshop.

  VHDL workshop Same as above but in VHDL.
 
  Understanding Synthesis Basics of timing analyses, "Cloud diagrams" to improve design understanding. The different phases within the synthesis process. Setting up I/O timing. How to write fast code. Architectural and layout dependant limitations. Synthesis scripting. 2 h lecture.
 
  101 beautiful uses of LFSRs. Still under development.
Linear Feedback Shift Registers. Maximum length LFSR and its dangers, psuedo-random generator, BIST, encoding, decoding. CRC and error checking. Parallel CRC computation. Encryption and decryption.
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